In order to obtain a high-speed operation and high-density integrated circuits (ICs) for the purpose of cost reduction, deep sub-micron CMOS processes like 90 nm, 65 nm, 45 nm have been introduced and implemented in many semiconductor IC devices. For those deep sub-micron processes, MOS transistors have to be scaled down (i.e., have minimum transistor dimensions decreased) and threshold voltage Vth of the transistors have to be lowered. However, the lowered threshold voltage results in significant sub-threshold leakage (i.e., leakage current present for transistor gate voltages below a threshold voltage) and therefore, semiconductor ICs based on such lowered threshold voltages consume more power in normal operation as well as power-down mode operation.
In the description, the term “standby” is used broadly and it includes a state wherein leakage current flows in a transistor while it is in substantially off state.
Conventional semiconductor ICs such as inverter logic gates, NAND logic gates and NOR logic gates are generally constituted by CMOS logic blocks with P-type transistors and N-type transistors. As the size of MOS transistors is scaled down, threshold voltage is lowered. In order to avoid an increase in standby leakage current, many schemes have been introduced.
FIG. 1A shows a simple inverter logic circuit, as an example of a conventional circuit found in semiconductor ICs. Referring to FIG. 1A, an inverter circuit 110 is comprised of a PMOS transistor 111 and an NMOS transistor 113 that are connected in series between a power supply line of high level voltage VDD and a ground line of low level voltage VSS. Transistors with different threshold voltages are currently offered by most semiconductor device manufacturers. For example, PMOS and NMOS transistors are available having “low” and “high” threshold values, sometimes referred to as a dual or multi-level threshold process. Typically “low” threshold transistors are used in circuits targeted for high speed applications whereas “high” threshold transistors are used in low power applications. Often semiconductor devices will have a combination of such low and high threshold transistors on the same device, depending on the particular circuit's application. In FIG. 1A, a typical inverter logic circuit is shown having the dual-threshold process where the threshold Vthp of the PMOS transistor 111 is low and the threshold Vthn of the NMOS transistor 113 is high.
In the inverter circuit 110, an input logic signal IN is fed to the gates of the PMOS transistor 111 and the NMOS transistor 113. A complementary version of the input logic signal IN is provided as an output signal OUT from a drain-connected node of the inverter circuit. When the input logic signal IN is a “low” logic state, standby current is reduced in a standby period, because of the high threshold Vthn of the NMOS transistor 113. However, such conventional dual threshold scheme has a drawback. When the input logic signal IN transitions from “low” logic state to “high” logic state, it causes a longer propagation delay.
FIG. 1B shows a CMOS inverter chain, as another example of conventional semiconductor ICs. Referring to FIG. 1 B, a CMOS inverter chain includes four inverters 121-124 with power switching PMOS and NMOS transistors 131 and 133. Each of the inverters 121 and 123 includes PMOS and NMOS transistors that are connected in series between a power supply line of high level voltage VDD and a virtual ground line of low level voltage VSSi. Each of the other inverters 122 and 124 includes PMOS and NMOS transistors that are connected in series between a virtual power supply line of high level voltage VDDi and a ground line of low level voltage VSS. The PMOS transistor 131 is connected between the power supply line (VDD) and the virtual power supply line (VDDi). The NMOS transistor 133 is connected between the virtual ground line (VSSi) and the ground line (VSS).
An input logic signal IN is fed to the gates of the PMOS and NMOS transistors of the first inverter 121. An output signal from the first inverter 121 is provided to the gates of the PMOS and NMOS transistors of the second inverter 122. Similarly, an output signal of the second inverter 122 is fed to the third inverter 123, the output signal of which is in turn fed to the fourth inverter 124. Power switch control signals SLEEP and SLEEP_b are fed to the gates of the PMOS and NMOS transistors 131 and 133, respectively. In a power down mode, the input signal IN stays at “low” logic level, and the power switch control signals SLEEP and SLEEP_b hold “high” and “low” logic levels, respectively, in order to shut off the two power switching PMOS and NMOS transistors 131 and 133. Those two control signals SLEEP and SLEEP_b must be generated and controlled in accordance with the external commands, like “power down mode entry” or “self refresh mode entry” in DRAM devices, for example. Therefore, in a normal operation mode, there can be still current leakage paths, because both of the power switching PMOS and NMOS transistors 131 and 133 are on.
U.S. Pat. No. 6,696,865 issued to Horiguchi et al. on Feb. 24, 2004 discloses a semiconductor IC device that is comprised of logic gates, each being provided with at least two MOS transistors. It includes a current control device for controlling a value of current flowing in the logic gate and operates in high and low power consumption modes.
U.S. Pat. No. 5,486,774 issued to Douseki et al. on Jan. 23, 1996 discloses a logic circuit includes a low-threshold logic circuit, a pair of power lines, a dummy power line, and a high-frequency logic circuit. The low-threshold logic circuit has a logic circuit comprised of a plurality of low-threshold MOS transistors. The pair of power lines supply power to the low-threshold logic circuit. The dummy power line is connected to one of power source terminals of the low-threshold logic circuit. The high-threshold control transistor is arranged between the dummy power line and the power line.
M. Horiguchi et al. disclose a switched-source-impedance CMOS circuit in their paper “Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 11, Novembeer 1993, pp. 1131-1135. In the CMOS circuit, a switched impedance element is inserted between the sources of MOS transistors and power lines to reduce the standby subthreshold currents.
The circuits disclosed in these documents use the specific “power saving mode” signals, like “SLEEP” and “SLEEP_b” or “CS” and “CS_b”, when power saving is specially required in the specific mode which is called by “sleep”, “power-down”, “self-refresh” or “standby” mode, for example. In the normal operation mode, there are still current leakage paths, resulting in current leakages and great total active power consumption.